1. Field of the Invention
This invention deals with static random access memory devices.
2. Description of the Prior Art
Static random access memory devices are well known in the prior art. One such prior art memory cell is described in U.S. Pat. No. 3,772,660 issued on an invention of Norman on Nov. 13, 1973 and assigned to Fairchild Camera and Instrument Corporation, the Assignee of this invention, and which is hereby incorporated by reference.
Broadly described, one type of random access memory (RAM) device comprises an array of cells, each cell capable of storing a single binary digit (bit). As described in the above-mentioned patent, one common form of prior art memory cell comprises a plurality of transistors connected to form a bistable flip-flop device. The state of the flip-flop is determined by the voltage levels (i.e. a logical 1 or a logical 0) on the bit and bit lines when the cell is written. The state of the cell (i.e., a logical 1 or a logical 0) is read without disturbing the contents of the cell by accessing the cell and examining, utilizing a suitable sense amplifier of well-known design, the voltage on the bit and bit lines.
It is highly desirable to minimize the cell size, thereby increasing the density of the memory device as a whole. In this manner, a greater number of memory cells are formed on a semiconductor substrate of a given size, thereby providing a memory cell of greater bit storage capacity. Alternatively, a memory cell of a given storage capacity may be formed on a smaller piece of semiconductor substrate, thereby decreasing the cost of the memory device.
Another prior art memory cell of reduced cell size as compared with the structure disclosed in the above-mentioned '660 patent is described in an article by R. Sud and K. C. Hardee entitled "16-K Static RAM Takes New Route to High Speed", Electronics, Sept. 11, 1980, pages 117-123, which is hereby incorporated by reference. The schematic diagram for this memory cell is shown in FIG. 1. Memory cell 10 is formed in a bistable flip-flop configuration. Resistors 11 and 12 are connected between a positive voltage source VCC on lead 13 and the gates of MOS transistors 15 and 16, respectively. The gates of N channel MOS transistors 15 and 16 are also connected to the drains of N channel MOS transistors 17 and 18, respectively. The source of transistor 15 is connected to the drain of transistor 18 and the source of transistor 16 is connected to the drain of transistor 17. The drains of transistors 15 and 16 are connected to a voltage supply V.sub.SS (typically ground) connected to lead 14. The gates of transistors 17 and 18 are connected to a word line 23, and the source of transistor 17 is connected via lead 21 to bit line 19. Similarly, the source of transistor 18 is connected via lead 22 to bit line 20.
The operation of cell 10 is as follows. When a logical 1 is to be written into cell 10, word line 23 is selected by applying a positive voltage thereto. A logical 1 is placed on bit line 19 and a logical 0 is placed on bit line 20. In this manner, N channel MOS transistors 17 and 18 are turned on, and the low bit signal is applied to the gate of transistor 16, thus turning transistor 16 off. The high signal applied to bit line 19 is applied through transistor 17 to the gate of transistor 15, thus turning transistor 15 on, thus applying ground (V.sub.SS) to the gate of transistor 16, thus maintaining transistor 16 off. With transistor 16 off, the positive voltage from VCC lead 13 is applied through resistor 11 to the gate of transistor 15, thus maintaining transistor 15 on. Word line 23 is then deselected by placing a low voltage thereon, thus turning off transistors 17 and 18. However, the low V.sub.SS signal on lead 14 remains applied to the gate of transistor 16 through conducting transistor 15, thus keeping transistor 16 turned off, which in turn causes the high VCC signal on lead 13 to be applied through resistor 11 to the gate of transistor 15, thus maintaining transistor 15 on. Thus, a logical 1 has been stored in cell 10.
In order to write a logical 0 in cell 10, the above operation is performed with the exception that a logical 0 is applied to bit line 19 and the logical 1 is applied to bit line 20. A logical one is applied to word line 23, thus turning on transistors 17 and 18. Thus, when writing a logical 0 into cell 10, the gate of transistor 15 receives a logical 0 from bit line 19 through transistor 17 and transistor 15 is turned off. Similarly, transistor 16 receives on its gate the logical 1 bit signal from bit line 20 and transistor 16 thus turns on. Word line 23 is then deselected thus causing transistors 17 and 18 to turn off. The V.sub.SS signal on lead 14 is applied to the gate of transistor 15 through transistor 16, thus keeping transistor 15 turned off. Because transistor 15 is turned off, the VCC signal from lead 13 is applied through resistor 12 to the gate of transistor 16, thereby maintaining transistor 16 turned on. Thus, a logical zero has been stored in cell 10.
In order to read cell 10, the word line 23 is selected and sense amplifiers (not shown) of a type well known in the art are connected to one or both of bit line 19 and bit line 20, thereby sensing the voltages present on the gates of transistors 15 and 16, respectively, thereby determining the state of cell 10.
In order to minimize the area on the semiconductor substrate required to form cell 10, cell 10 is formed utilizing diffused N+ regions as the source and drain regions of N channel MOS transistors 15, 16, 17 and 18, V.sub.SS lead 14, and leads 21 and 22, as well as the interconnecting lead 30 between transistor 16 and transistor 17. A layer of polycrystalline silicon (often referred to as "poly") is used to form resistors 11 and 12, VCC lead 13, word line 23, and the gates of transistors 15, 16, 17 and 18. The three contacts between the N+ diffused regions and the poly regions are shown in FIG. 1 as "Xs" 25, 26 and 27. Bit lines 19 and 20 are formed of metal, typically aluminum or an alloy of aluminum. The contacts from poly leads 21 and 22 to bit line 19 and bit line 20 are shown in FIG. 1 as squares 28 and 29, respectively.
FIG. 2 is a schematic diagram of a plurality of cells illustrating the effect of resistances associated with lead V.sub.SS in FIG. 1 on the stability of the data stored within the cells of a memory array. Memory array 40 is comprised of memory cells 1 through n. Resistors R1, R2, through Rn represent the finite resistance values of V.sub.SS lead 14 associated with each cell 1, 2 through n. When, as in the case of the circuit of FIG. 1, a diffused region is used as V.sub.SS lead 14, the resistances R1, R2 through Rn are rather high, because the sheet resistance of diffused regions are generally at least 20 ohms/square. Typically, the resistance values of resistors R1, R2 through Rn are approximately 300 ohms, and the current which must be sunk by V.sub.SS lead 14 when a selected cell 1 through n is accessed is approximately 250 microamps. Of importance, resistance R1 carries the current I.sub.1 required to read cell 1, resistance R2 carries the currents I.sub.1 I.sub.2 required to read cells 1 and 2, respectively, and resistance Rn carries the currents I.sub.1, I.sub.2 . . . I.sub.N. Thus, for example, when N=4, where N represents the number of cells in the circuit of FIG. 2, the voltage drop across the series resistance of V.sub.SS lead 14 is approximately 75 millivolts for cell 1, and a correspondingly larger amount for cells 2 through 4, with a 300 mV voltage difference across resistor Rn which is a 300 mV difference in the voltages which are available for application to the gate of transistor 15 (through transistor 16) and the gate of transistor 16 (through transistor 15). During reading of the cell, this offset voltage causes a logical zero level on the gate of transistor 16 which is 300 mV greater than the logical zero level on the gate of transistor 15, thus possibly causing, during the read operation, the undesired destruction of data stored within the cell.